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Std.Tactic.BVDecide.Bitblast.BVExpr.Circuit.Impl.Carry

This module contains the implementation of a circuit to determine whether a certain addition would overflow. This is provided separately from the addition circuit for two reasons:

  1. Determining whether an overflow will occur does not require to build a full ripple carry adder.
  2. Other operations such as unsigned less than may be implemented in terms of overflow detection.
  • w : Nat
  • vec : aig.BinaryRefVec self.w
  • cin : aig.Ref
Instances For
    @[irreducible]
    def Std.Tactic.BVDecide.BVExpr.bitblast.mkOverflowBit.go {α : Type} [Hashable α] [DecidableEq α] {w : Nat} (aig : Std.Sat.AIG α) (lhs : aig.RefVec w) (rhs : aig.RefVec w) (curr : Nat) (cin : aig.Ref) :
    Equations
    • One or more equations did not get rendered due to their size.
    Instances For
      @[irreducible]
      theorem Std.Tactic.BVDecide.BVExpr.bitblast.mkOverflowBit.go_le_size {α : Type} [Hashable α] [DecidableEq α] {w : Nat} {curr : Nat} {aig : Std.Sat.AIG α} {cin : aig.Ref} {lhs : aig.RefVec w} {rhs : aig.RefVec w} :
      aig.decls.size (Std.Tactic.BVDecide.BVExpr.bitblast.mkOverflowBit.go aig lhs rhs curr cin).aig.decls.size
      @[irreducible]
      theorem Std.Tactic.BVDecide.BVExpr.bitblast.mkOverflowBit.go_decl_eq {α : Type} [Hashable α] [DecidableEq α] {w : Nat} {curr : Nat} {aig : Std.Sat.AIG α} {cin : aig.Ref} {lhs : aig.RefVec w} {rhs : aig.RefVec w} (idx : Nat) (h1 : idx < aig.decls.size) (h2 : idx < (Std.Tactic.BVDecide.BVExpr.bitblast.mkOverflowBit.go aig lhs rhs curr cin).aig.decls.size) :
      (Std.Tactic.BVDecide.BVExpr.bitblast.mkOverflowBit.go aig lhs rhs curr cin).aig.decls[idx] = aig.decls[idx]
      instance Std.Tactic.BVDecide.BVExpr.bitblast.mkOverflowBit.instLawfulOperatorOverflowInput {α : Type} [Hashable α] [DecidableEq α] :
      Std.Sat.AIG.LawfulOperator α Std.Tactic.BVDecide.BVExpr.bitblast.OverflowInput Std.Tactic.BVDecide.BVExpr.bitblast.mkOverflowBit
      Equations
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